The present invention is directed generally to a semiconductor storage system, and more particularly, to a semiconductor storage system capable of high-speed access, while avoiding read/write errors resulting from defects present in elements of a constituent semiconductor storage element array.
In recent years, semiconductor memory manufacturing technology has advanced. This advancement has made it possible to provide a semiconductor memory based storage module as an external storage system of a computer. External storage systems have hitherto comprised one or more fixed disk drives. Semiconductor memory based external storage systems are exemplified by RAMSTOR made by Western Automation Corp. in USA or disclosed in Japanese Patent Laid-Open No. 32420/1990 (Japanese Patent Application No. 181873/1988).
FIG. 1 is a schematic block diagram showing one example of the construction of such a conventional semiconductor storage system. Referring to FIG. 1, the numeral 1 represents a semiconductor storage element array; 2 a data bus; 3 a DRAM controller; 4 an address bus; 5 a DMA controller; 6 an I/F (interface) control module; 7 an ECC circuit; and 8 a microprocessor.
The operation thereof will hereinafter be described with reference to the accompanying drawings. A command given from a host computer 16, also called a host system, is input to the I/F control module 6 for controlling a transfer and receipt thereof. The command is thereafter decoded by the microprocessor 8 for controlling the DMA controller and the interface control module. The command is executed thereby. One important command is a data transfer command, and the data transfer is executed by the DMA controller 5. The microprocessor 8 calculates an actual data transfer start address and a data transfer quantity from a transfer data quantity and a transfer start logical address specified by the host system. The data transfer start address and the data transfer quantity are imparted to the DMA controller 5. If a defect occurs in the semiconductor storage element array 1, the defect is detected by self-diagnosis at the starting time. Calculations are effected to eliminate the defect.
The DRAM controller 3 controls data read/write timing. When reading the DRAM controller 3 reads data from the semiconductor storage element array 1 in which the data is stored. When writing, DRAM controller 3 gives a write timing signal. An address for read data or write data is given via the address bus 4. The read data or the write data is transmitted via the data bus 2. The ECC circuit 7 corrects the errors in the read or write data, and reading thereof is then effected. The ECC circuit 7 generates and adds error correction data to the writer data. The error correction data is written together with the write data.
Disclosed in Japanese Patent Laid-Open No. 32420/1990 (Japanese Patent Application No. 181873/1988) is a technique by which an interface between the outside and a semiconductor file device, i.e., a modulation/demodulation circuit incorporated into the system is compatible with the conventional magnetic disk drive. Based on this technique, the I/F control module 6, the ECC circuit 7 or a defect replacement function are entrusted to the controller itself for the magnetic disk.
However, this type of conventional semiconductor device constructed in the manner described above, presents a problem. It takes much time to replace deteriorated addresses and defective data by use of the ECC circuit 7, i.e., several tens of .mu.s are required. This produces a rate-determining factor, thereby probably causing a drop of data transfer rate to the host system. To avoid this drop, it is required to maintain, within the semiconductor storage system, a 1.5-fold higher internal transfer rate than external transfer rate between the host system and the semiconductor storage system. It is also required that an FIFO (first-in and first-out) buffer memory having a capacity as large as 1 MB be provided to properly perform the transfer between the outside and the inside at different transfer rates.
The following is a description of additional inconveniences incidental to the technique disclosed in Japanese Patent Laid-Open No. 32420/1990 (Japanese Patent Application No. 181873/1988). An interface identical to the interface of the conventional magnetic disk drive is employed. As a result, initialization is needed every time the power supply is turned ON to establish the replacement address. The initialization requires much time. Besides, a data area corresponding to a data gap of the magnetic disk becomes redundant. The replacement process is effected on a track or a sector unit basis. Thus the portions undergoing the replacement process are larger than the defect.
There arises a further problem incidental to the conventional device. When an error is produced during operation, a soft error restorable by the ECC circuit may, over time, become a hard error unrestorable by the ECC circuit. Such a defect in turn damages the data. Due to the reasons outlined above, the number of allowable defects for a single device is limited.